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1、设计过程 验证电路逻辑 编译网表版图设计过程 平面布局 布置 布线 预制门阵列芯片 验证 流程图 实例school of phyebasics of ic layout design1school of phyebasics of ic layout design2school of phyebasics of ic layout design3school of phyebasics of ic layout design4school of phyebasics of ic layout design5school of phyebasics of ic layout design6sch
2、ool of phyebasics of ic layout design7school of phyebasics of ic layout design8school of phyebasics of ic layout design9适用抽象层次的比较school of phyebasics of ic layout design10school of phyebasics of ic layout design11school of phyebasics of ic layout design12school of phyebasics of ic layout design13sch
3、ool of phyebasics of ic layout design14school of phyebasics of ic layout design15school of phyebasics of ic layout design16school of phyebasics of ic layout design17school of phyebasics of ic layout design18school of phyebasics of ic layout design19school of phyebasics of ic layout design20school of
4、 phyebasics of ic layout design21school of phyebasics of ic layout design22school of phyebasics of ic layout design23school of phyebasics of ic layout design24school of phyebasics of ic layout design25school of phyebasics of ic layout design26school of phyebasics of ic layout design27school of phyeb
5、asics of ic layout design28school of phyebasics of ic layout design29门级module array_buf(in,out,en);input 3:0 in;output 4:0 out;input en;/*instance*/bufif1 array_buf0(out0,in0,en);bufif1 array_buf1(out1,in1,en);bufif1 array_buf2(out2,in2,en);bufif1 array_buf3(out3,in3,en);endmoduleRTL级module mux(out,
6、a,b,sel);output out;input a,b,sel;assign out=(sel=0)?a:bendmodule行为级/算法级sum=0;for(i=0;i7;i=i+1)beginsum=sum+Ai;endsum_out=sum;school of phyebasics of ic layout design30school of phyebasics of ic layout design31mudule dff_pos(data,clk,q);input data,clk;output q;reg q;always(posedge clk)q=data;endmodu
7、le 模块定义行端口类型说明数据类型说明 描述体 结束行school of phyebasics of ic layout design32模块描述模块定义行端口类型说明数据类型说明描述体结束行过程块1过程块2.过程语句（initial/always）块语句（begin-end/fork-join）school of phyebasics of ic layout design33school of phyebasics of ic layout design34school of phyebasics of ic layout design35school of phyebasics of
8、ic layout design36 测试信 clk 号和测 试条件 的控制 resetcounter4 被测模out 块对测 试信号 的响应counter4 testbenchschool of phyebasics of ic layout design37 school of phyebasics of ic layout design38school of phyebasics of ic layout design39school of phyebasics of ic layout design40Cadence LDV 5.1school of phyebasics of ic
9、layout design41school of phyebasics of ic layout design42counter4 waveformcounter4 testbenchschool of phyebasics of ic layout design43school of phyebasics of ic layout design44school of phyebasics of ic layout design45school of phyebasics of ic layout design46school of phyebasics of ic layout design
10、47inv2inv4inv81x2x4xschool of phyebasics of ic layout design48Clock Tree Networkschool of phyebasics of ic layout design491、读入网表，跟foundry提供的标准单元库和 Pad 库以及宏模块库进行映射；2、整体布局，规定了芯片的大致面积和管脚位置以及宏单元位置等粗略的信息；3、读入时序约束文件，设置好 timing setup 菜单，为后面进行时序驱动的布局布线做准备；4、详细布局，力求使后面布线能顺利满足布线布通率 100%的要求和时序的要求；5、时钟树综合，为了降低
11、clock skew 而产生由许多 buffer单元组成的“时钟树”；6、布线，先对电源线和时钟信号布线，然后对信号线布线，目标是最大程度地满足时序；7、为满足 design rule 从而 foundry 能成功制造出该芯片而做的修补工作，如填充一些 dummy等。这七大步骤是基本的流程，其中每大步骤里面包含很多小的步骤。P&R flowschool of phyebasics of ic layout design50P&R flowschool of phyebasics of ic layout design51P&R flowschool of phyebasics of ic la
12、yout design52P&R flowschool of phyebasics of ic layout design53school of phyebasics of ic layout design54school of phyebasics of ic layout design55school of phyebasics of ic layout design56school of phyebasics of ic layout design57CycloneIII EP3C120 FPGA Xilinx Virtex5 FPGA school of phyebasics of i
13、c layout design58chip verification flow school of phyebasics of ic layout design59school of phyebasics of ic layout design60school of phyebasics of ic layout design61单元布置数据布线数据晶体管级版图GDSII文件融合GDSII文件产生GDSIILogic NetlistDRCLVSDRC及LVS检查school of phyebasics of ic layout design62Logic DesignLogic SynthesisFloorplanP&R ToolsGDS IIDRC+LVSFinal Chip DataDigital LibrariesTiming ChecksNetlistTiming ChecksGDSIIdigital ic design flowschool of phyebasics of ic layout design63a layout example of digital ic
集成电路版图设计基础第三章：数字IC版图
