《集成电路设计CAD-EDA工具实用教程1-Spe课件》由会员分享，可在线阅读，更多相关《集成电路设计CAD-EDA工具实用教程1-Spe课件（27页珍藏版）》请在装配图网上搜索。
1、单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,共27页,Spectre,Verilog,混合信号仿真,共27页,1,几家,EDA,软件,公司,1,、,Cadence,2,、,Synopsys,（收购,Avanti,）,3,、,Mentor Graphics,4,、,Silvaco,5,、,SpringSoft,共27页,2,SPICE,仿真器,SPICE,:,a general-purpose analog circuit simulator developed by the University of California,Berkeley.It is
2、used for nonlinear DC,nonlinear transient,and linear AC analysis.,Hspice,:a general-purpose circuit simulator from Avanti.It has an extensive set of built-in device models,including models for small geometry,MOSFETs,and,MESFETs,.The program is compatible with SPICE input formats.Cadence supports a l
3、ibrary of primitives and a full interface for,Hspice,.,Spectre,:SPICE-alike analog simulator developed by Cadence.,共27页,3,高精度,模拟,/,射频,电路仿真器,1,、,Spectre/SpectreRF,(Cadence),2,、,Hspice/HspiceRF,(Synopsys),3,、,Ads(Agilent,主要针对,RF),4,、,Eldo,(Mentor Graphics),5,、,Saber(Synopsys),共27页,4,数模,混合信号,仿真器,1,、,Sp
4、ectre-Verilog,(Cadence),2,、,SMASH(Dolphin Integration),3,、,Eldo,(Mentor Graphics),4,、,Harmony(,Silvaco,),5,、,Saber(Synopsys),Why Mixed-Signal Simulation?,共27页,5,System in the Real World,共27页,6,Mostly Applied Method of Mixed-Signal Design,系统分成若干个芯片，每个芯片分开设计，再经电路板整合。,或者用,SoC,实现。,共27页,7,IntegratedMixed
5、-Signal Design,共27页,8,Mixed-Signal Simulator,的基本结构,以模拟电路仿真器为核心,在处理数模混合电路时将数字部分等效为相应的简化的模拟电路、或,者采用解析函数来表示逻辑模块的行为，然后对整个系统采用模拟电路,的方法进行模拟。优点：模拟结果精确、能处理的电路规模比较大，模,拟速度也有显著提高。缺点：比逻辑模拟器还是慢很多。,同时包含模拟和数字两个仿真核,处理速度快，能处理的电路规模极大，但需要解决模拟仿真核和数字,仿真核之间的通信问题；另外，由于数字逻辑仿真器和模拟仿真器的输,入、输出数据是不一样的，还必须在模拟仿真核和数字仿真核之间实现,模拟信号和数
6、字信号的相互转换。,Q&A,共27页,9,Creating Analog Block,Create the schematic view of analog block,and create a symbol view for cell use,共27页,10,Creating Digital Block,共27页,11,Creating a Mixed-Signal Schematic,共27页,12,Create,Config,View for Simulation,The mixed-signal simulation hierarchy is controlled by,Hierarc
7、hy-Editor,which must be defined with,config,view,cell name is top circuit name for,simulation,view name will be set as,config,Use Create New File to create a new,config,view with Hierarchy-Editor,共27页,13,Set New Configuration,1.Choose,Use Template sample information,2.Choose,spetreVerilog,1,2,3,3.Ch
8、ange the view name to,schematic,for simulation,4.Click,OK,共27页,14,Open the Schematic Version of,Config,View,Open the schematic version of the,config,view of,mix,from the Library manager,共27页,15,Set Block Partition,开启,hierarchy editor,设定所使用的,cell view,显示所使用的,cell view,及其颜色设定,Schematic editor,中,的,Hier
9、archy-Editor,及,Mixed-Signal,两项,Menu,是由菜单,Tools-Mixed Signal,Opts.,而产生的,共27页,16,Check Block Partition,Change analog&digital stop views to match the stop views in your hierarchy editor(as below),共27页,17,Check Partition Results,设定显示的颜色及项目,显示所有模块划分的结果,显示模拟电路模块,显示数字电路模块,显示混合信号电路模块,显示无法归类的电路模块,清除所有显示内容,共2
10、7页,18,Partition Requirement,The design must contain at least one analog component.,The design must contain at least one digital component.,There must be with at least one interface net.,Analog stimuli defined in the analog stimuli file cannot be used to drive digital net.,Digital stimuli defined in
11、the digital stimuli file can not be used to drive analog net.,Any interface net must be identified before,netlisting,.,共27页,19,Setup the analog/digital interface,Select:,Mixed-Signal-Interface Elements-Instance,this tool is used to configure how,the digital block reads analog inputs and how digital
12、outputs are seen by analog cells(effective A/D and D/A).,共27页,20,Setup the analog/digital interface,MOS_a2d:A2D_V0,低电平,A2D_V1,高电平,A2D_TX,：,voltage between V0 and V1 after TX will yield a logic X,MOS_d2a,：,Model Parameters,D2A_VL:input low voltage,D2A_VH:input high voltage,D2A_TR:rise time for low to
13、 high,D2A_TF:fall time for high to low,共27页,21,Setup Menu in Analog Environment,With Setup window to define simulation,initialization setup,Choose the simulator,Define device model library,Define temperature,共27页,22,Choosing Simulator/Directory/Host,选择,SpectreVerilog,共27页,23,Choose Analysis Type,Inv
14、oke the analysis,setting window,For Mixed-Signal,simulation,only,tran,is meaningful,Set the simulation time,Check this box to enable this simulation,共27页,24,Submit the Simulation,Execute the simulation job with Run,or create the,netlist,with,Netlist,start simulation,共27页,25,Results,数字输出,数字,/,模拟输入,模拟输出,共27页,26,THANK YOU!,共27页,27,
集成电路设计CAD-EDA工具实用教程1-Spe课件
