计算机设计与实践-32位ALU设计

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1、单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,32,位,ALU,设计,Verilog HDL,语言,module alu(alu_da,alu_db,alu_clt,alu_shift,alu_zero_out,overflow_out,alu_dc,);,input 31:0alu_da;,input 31:0alu_db;,input 3:0alu_clt;,input 4:0alu_shift;,output reg alu_zero_out;,out

2、put reg overflow_out;,output reg 31:0alu_dc;,wire alu_zero;,wire overflow;,wire 31:0alu_and;/,与结果,wire 31:0alu_or;/,或结果,wire 31:0alu_xor;/,异或结果,reg 31:0alu_sll;/,左移结果,reg 31:0alu_srl;/,右移结果,reg 31:0alu_sra;/,算数右移,wire 31:0alu_add;/,加减运算结果,wire c2;/,加法器进位输出,reg Sub;/,加法器控制端,wire 31:0alu_db_n;/b,取非运算,

3、reg 31:0alu_db_mux;/b,的加减选择运算,wire ci;/,进位输出,always(*),begin,case(alu_clt),0:alu_dc=alu_and;/,逻辑与运算,1:alu_dc=alu_or;/,逻辑或运算,2:alu_dc=alu_xor;/,逻辑异或运算,3:alu_dc=alu_sll;/,左移运算,4:alu_dc=alu_srl;/,右移运算,5:alu_dc=alu_sra;/,算数右移运算,6:/,无符号加运算,begin,Sub=0;,alu_dc=alu_add;,alu_zero_out=0;,overflow_out=0;,end,

4、7:/,无符号减运算,begin,Sub=1;,alu_dc=alu_add;,alu_zero_out=0;,overflow_out=0;,end,8:/,有符号加运算,begin,Sub=0;,alu_dc=alu_add;,alu_zero_out=alu_zero;,overflow_out=overflow;,end,9:/,有符号减运算,begin,Sub=1;,alu_dc=alu_add;,alu_zero_out=alu_zero;,overflow_out=overflow;,end,10:/,无符号小于置,1,运算,begin,Sub=1;,if(c2=0),alu_d

5、c=1;,else,alu_dc=0;,end,11:/,有符号小于置,1,运算,begin,Sub=1;,if(alu_add31=1),alu_dc=1;,else,alu_dc=0;,end,default:alu_dc=alu_dc;,endcase,end,assign alu_and=alu_da,assign alu_or=alu_da|alu_db;,assign alu_xor=alu_daalu_db;,always(*),begin,case(alu_shift),0:alu_sll=alu_da;,1:alu_sll=alu_da1;,2:alu_sll=alu_da2

6、;,3:alu_sll=alu_da3;,4:alu_sll=alu_da4;,5:alu_sll=alu_da5;,6:alu_sll=alu_da6;,7:alu_sll=alu_da7;,8:alu_sll=alu_da8;,9:alu_sll=alu_da9;,10:alu_sll=alu_da10;,11:alu_sll=alu_da11;,12:alu_sll=alu_da12;,13:alu_sll=alu_da13;,14:alu_sll=alu_da14;,15:alu_sll=alu_da15;,16:alu_sll=alu_da16;,17:alu_sll=alu_da1

7、7;,18:alu_sll=alu_da18;,19:alu_sll=alu_da19;,20:alu_sll=alu_da20;,21:alu_sll=alu_da21;,22:alu_sll=alu_da22;,23:alu_sll=alu_da23;,24:alu_sll=alu_da24;,25:alu_sll=alu_da25;,26:alu_sll=alu_da26;,27:alu_sll=alu_da27;,28:alu_sll=alu_da28;,29:alu_sll=alu_da29;,30:alu_sll=alu_da30;,31:alu_sll=alu_da31;,def

8、ault:alu_sll=alu_da;,endcase,end,always(*),begin,case(alu_shift),0:alu_srl1;,2:alu_srl2;,3:alu_srl3;,4:alu_srl4;,5:alu_srl5;,6:alu_srl6;,7:alu_srl7;,8:alu_srl8;,9:alu_srl9;,10:alu_srl10;,11:alu_srl11;,12:alu_srl12;,13:alu_srl13;,14:alu_srl14;,15:alu_srl15;,16:alu_srl16;,17:alu_srl17;,18:alu_srl18;,1

9、9:alu_srl19;,20:alu_srl20;,21:alu_srl21;,22:alu_srl22;,23:alu_srl23;,24:alu_srl24;,25:alu_srl25;,26:alu_srl26;,27:alu_srl27;,28:alu_srl28;,29:alu_srl29;,30:alu_srl30;,31:alu_srl31;,default:alu_srl=alu_da;,endcase,end,always(*),begin,case(alu_shift),0:alu_sra=alu_da;,1:alu_sra=alu_da31,alu_da31:1;,2:

10、alu_sra=2alu_da31,alu_da31:2;,3:alu_sra=3alu_da31,alu_da31:3;,4:alu_sra=4alu_da31,alu_da31:4;,5:alu_sra=5alu_da31,alu_da31:5;,6:alu_sra=6alu_da31,alu_da31:6;,7:alu_sra=7alu_da31,alu_da31:7;,8:alu_sra=8alu_da31,alu_da31:8;,9:alu_sra=9alu_da31,alu_da31:9;,10:alu_sra=10alu_da31,alu_da31:10;,11:alu_sra=

11、11alu_da31,alu_da31:11;,12:alu_sra=12alu_da31,alu_da31:12;,13:alu_sra=13alu_da31,alu_da31:13;,14:alu_sra=14alu_da31,alu_da31:14;,15:alu_sra=15alu_da31,alu_da31:15;,16:alu_sra=16alu_da31,alu_da31:16;,17:alu_sra=17alu_da31,alu_da31:17;,18:alu_sra=18alu_da31,alu_da31:18;,19:alu_sra=19alu_da31,alu_da31:

12、19;,20:alu_sra=20alu_da31,alu_da31:20;,21:alu_sra=21alu_da31,alu_da31:21;,22:alu_sra=22alu_da31,alu_da31:22;,23:alu_sra=23alu_da31,alu_da31:23;,24:alu_sra=24alu_da31,alu_da31:24;,25:alu_sra=25alu_da31,alu_da31:25;,26:alu_sra=26alu_da31,alu_da31:26;,27:alu_sra=27alu_da31,alu_da31:27;,28:alu_sra=28alu

13、_da31,alu_da31:28;,29:alu_sra=29alu_da31,alu_da31:29;,30:alu_sra=30alu_da31,alu_da31:30;,31:alu_sra=31alu_da31,alu_da31;,default:alu_sra=alu_da;,endcase,end,assign alu_db_n=alu_db;/,加减运算,always(*),begin,if(Sub=1),alu_db_mux=alu_db_n;,else,alu_db_mux=alu_db;,end,alu_32 alu_32_1(alu_add,alu_da,alu_db_

14、mux,Sub,c2);,assign overflow=alu_da31,assign alu_zero=(alu_add0|alu_add1|alu_add2|alu_add3|alu_add4|alu_add5|alu_add6|alu_add7|alu_add8|alu_add9|alu_add10|alu_add11|alu_add12|alu_add13|alu_add14|alu_add15|alu_add16|alu_add17|alu_add18|alu_add19|alu_add20|alu_add21|alu_add22|alu_add23|alu_add24|alu_a

15、dd25|alu_add26|alu_add27|alu_add28|alu_add29|alu_add30|alu_add31);,endmodule,module alu_32(f32,x32,y32,ciii,c2);/32,位加法器先行进位加法器,input 32:1x32;,input 32:1y32;,input ciii;/,进位输入,output 32:1f32;,output c2;/,进位输出,wire c1;,wire 2:1p;,wire 2:1g;,alu_16 alu_16_1(g1,p1,f3216:1,x3216:1,y3216:1,ciii);,alu_16

16、alu_16_2(g2,p2,f3232:17,x3232:17,y3232:17,c1);,assign c1=g1|p1,assign c2=g2|p2,endmodule,module alu_16(gmm,pmm,f16,x16,y16,cii);/16,位加法器先行进位加法器,input 16:1x16;,input 16:1y16;,input cii;,output 16:1f16;,output gmm,pmm;,wire 4:1c;,wire 4:1p;,wire 4:1g;,jiafaqi_4 alu_4_1(g1,p1,f164:1,x164:1,y164:1,cii);,jiafaqi_4 alu_4_2(g2,p2,f168:5,x168:5,y168:5,c1);,jiafaqi_4 alu_4_3(g3,p3,f1612:9,x1612:9,y1612:9,c2);,jiafaqi_4 alu_4_4(g4,p4,f1616:13,x1616:13,y1616:13,c3);,cla_4 cl_4_1(c,p,g,cii);,assign pmm=p4,a